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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81492

    Title: 以基本類比電路架構為基礎的佈局自動化 工具;An Analog Layout Generator with Structure-Based Methodology
    Authors: 陳宇嫻;Chen, Yu Hsien
    Contributors: 電機工程學系
    Keywords: 佈局自動化;類比電路
    Date: 2019-08-19
    Issue Date: 2019-09-03 15:57:26 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 現今的類比電路佈局大多還是靠人工的方式產生,為了要加速類比電路設計的速度,近年來類比電路自動化是一項熱門的研究,不過由於類比電路的敏感性,如何設定許多的佈局限制來減少非理想效應的發生顯得非常的重要,但是在目前的設計流程中,大多數佈局限制都還是要靠設計者手動給定,需要花費大量的設計時間,使用以模板為基礎(template-based)的方式是個自動化考慮設計限制的好方法,不過有新的設計或新的製程時,都需要重新做調整與設計,因此,一個整合了擺置、繞線以及生成佈局限制的佈局自動化工具應該可以有效地縮短設計時間。
    ;Currently, the layouts of analog circuits are often generated manually. In order to speed up analog design cycles, analog layout automation is a popular research in recent years. Due to the sensitivity of analog circuits, it is important to consider non-ideal effects in design stage by setting proper layout constraints. However, most of the layout constraints are given manually in current design flow, which requires lots of time. Template-based layout generation is a possible approach to consider the design constraints automatically, but considerable development efforts are required for each new design or technology. Therefore, an integrated layout automation tool including placement, routing and constraint generation could be helpful to reduce design time.
    This thesis proposes a structure-based methodology for analog layout generation. This methodology starts from a structure analysis that divides the circuit netlist into several building blocks automatically. It can help to reduce the dependence on users’ input and generate corresponding design constraints for the succeeding layout steps. With the help from structure analysis, the layouts of those analog structures are generated, placed, and routed automatically with proper constraints. As shown in the demo cases, the proposed flow is able to generate the required layout accurately without users’ intervention and still keeps the post-layout performance within specifications.
    Appears in Collections:[電機工程研究所] 博碩士論文

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