實現類比電路仿真的波動數位濾波器架構生成與模擬;On WDF Structure Synthesis and Simulation for Analog Circuit Emulation

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題名:	實現類比電路仿真的波動數位濾波器架構生成與模擬;On WDF Structure Synthesis and Simulation for Analog Circuit Emulation
作者:	蔡季軒;Tsai, Ji-Xuan
貢獻者:	電機工程學系
關鍵詞:	類比電路;仿真
日期:	2019-08-19
上傳時間:	2019-09-03 15:58:38 (UTC+8)
出版者:	國立中央大學
摘要:	隨著製程技術發展日益成熟，單晶片系統( System on Chip , SOC )已成為設計的主流。由於在單晶片系統架構當中包含了數位電路與類比電路，系統的整合與驗證仍然是一個很大的挑戰。數位電路已經有了FPGA這種快速且低成本進行電路驗證與仿真的平台，而目前尚未有一個成熟的針對類比或是混訊電路的仿真器可以很完美的解決混訊驗證的問題。本篇論文利用波動數位濾波器(Wave Digital Filter, WDF)的原理，將類比電路對映到數位電路上，進而在FPGA上實現類比電路的仿真。儘管WDF理論被證明是一個可以用來仿真類比電路的有效方法，但是尚未有一個完整而有效的方法可以將結構複雜的電路轉換成對應的WDF架構。本篇論文引入了J型配線器(J-type Adaptor)的概念來解決複雜電路的環狀結構。有了J型配線器後，我們提出了一個自動化的流程可以將各種不同的類比電路轉換為WDF架構，此外還針對轉換出的架構提出了深度優化演算法，進而縮短關鍵路徑(Critical Path)。在優化流程結束後，也會在我們建構的MATLAB環境中模擬WDF架構的行為以驗證架構的正確性，並且可以得到有效的資訊提供給後續的FPGA硬體實現流程。從實驗結果可以看出，本篇論文所提出的流程可以針對實驗電路轉換出正確的WDF架構且縮短其關鍵路徑。 ;With the development of semiconductor process technology, system-on-chip (SOC) has become the mainstream of design style. However, system integration and verification are still big challenges for SOC designs including digital circuits and analog circuits. FPGA emulation is a fast and low-cost solution for verifying digital circuits. For analog/mixed-signal circuits, there is still no mature emulator to solve the problem of mixed-signal verification. In this thesis, Wave Digital Filter (WDF) is adopted to map analog circuits to digital circuits for the analog circuit emulation on FPGA. Although classical WDF theory was proved as a solid method to emulate analog circuits, there is no complete and efficient approach for converting complex circuit structures into corresponding WDF structures. In this thesis, we adopt the concept of J-type adaptor to handle the loop structures of complex circuits. With the new J-type adaptor, an automatic flow is proposed to convert various analog circuits into WDF structures. Furthermore, a depth optimization algorithm is also proposed to reduce the critical path of generated WDF structures. After optimization, the WDF structure will be simulated in the proposed MATLAB environment to verify its correctness and get some useful information for the following FPGA implementation flow. As shown in the demo cases , the proposed flow is able to provide accurate WDF structures with minimized path length for those cases.
顯示於類別:	[電機工程研究所] 博碩士論文

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