本論文電路使用TSMC 40 nm 1P9M (TN40G) CMOS 製程來實現，電路操作電壓為0.9 V，輸入參考訊號頻率為100 MHz，輸出時脈訊號頻率為6 GHz。次取樣鎖相迴路的展頻時脈產生器的部份則是使用三角波調變式的展頻可以得到21 dB的電磁干擾抑制量。電路所占面積為0.13 mm2，晶片所佔面積為1.11 mm2。 ;A 6 GHz SATA-III spread-spectrum clock generator in sub-sampling loop structure is presented in this thesis. It uses triangular spread wave and down-spread technique. In structure, the loop without divider has wider loop bandwidth compared with phase-locked loop, so it has better jitter performance. In spread-spectrum clock, we replaced external reference signal of sub-sampled phase detector with that signal triggered by voltage-controlled oscillator. The design makes input signals of sub-sampled phase detector, including the signal triggered by voltage-controlled oscillator and differential output of voltage-controlled oscillator, come from voltage-controlled oscillator and lose lock in inherent direction. Therefore, if we carefully adjust the direction and monitor turning points, we can perform smooth triangular wave spread spectrum. The design gets more advantages of chip area, power, EMI reduction and jitter performance because the design has larger loop bandwidth and simple architecture. In addition, we also adopt the current mode capacitor amplification to save more chip area.
The proposed spread-spectrum clock generator circuit is fabricated in TSMC 40nm 1P9M CMOS process at 6 GHz operating frequency. The supply voltage is 0.9 V. The input reference frequency is 100 MHz. The reduction of electromagnetic interference is 21 dB with the spread-spectrum mechanism modulated by triangular wave. The chip area is 1.11 mm2. The core area is 0.13 mm2.