English  |  正體中文  |  简体中文  |  Items with full text/Total items : 68069/68069 (100%)
Visitors : 23221704      Online Users : 166
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81526


    Title: 應用於SATA III之 6 GHz 展頻時脈迴路;A 6 GHz SATA-III Spread Spectrum Clock Generator
    Authors: 楊育銜;Yang, Yu-Sian
    Contributors: 電機工程學系
    Keywords: 展頻時脈;時脈;次取樣鎖相迴路;鎖相迴路;spread spectrum clock generator;clock generator;sub-sampling phase-locked loop;phase-locked loop
    Date: 2019-08-20
    Issue Date: 2019-09-03 16:00:12 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本論文提出了以次取樣鎖相迴路為架構的6 GHz展頻時脈電路設計,符合SATA III之展頻時脈規格,使用三角波向下展頻;架構上,在次取樣鎖相迴路中,由於缺少除頻器而具有較大迴路頻寬,因此擁有較佳的抖動量;在次取樣檢測器中,以壓控振盪器取樣輸入參考訊號,替換原本外接輸入參考訊號,與次取樣檢測器另一組輸入端點,壓控振盪器差動輸出,皆為同源訊號而失鎖往固定方向,利用此狀態來對時脈展頻,並使用適應器偵測三角波波峰與波谷的頻率,適時調整追鎖方向,來實現平滑三角波展頻電路,因此電路同時具有較大迴路頻寬與簡易架構兩大優勢,而具有較小核心面積、功耗和較大的電磁干擾抑制量與較佳的抖動量;另外,為了減少類比濾波器面積大小,本論文使用電流式電容放大技術來大量縮減面積。

    本論文電路使用TSMC 40 nm 1P9M (TN40G) CMOS 製程來實現,電路操作電壓為0.9 V,輸入參考訊號頻率為100 MHz,輸出時脈訊號頻率為6 GHz。次取樣鎖相迴路的展頻時脈產生器的部份則是使用三角波調變式的展頻可以得到21 dB的電磁干擾抑制量。電路所占面積為0.13 mm2,晶片所佔面積為1.11 mm2。
    ;A 6 GHz SATA-III spread-spectrum clock generator in sub-sampling loop structure is presented in this thesis. It uses triangular spread wave and down-spread technique. In structure, the loop without divider has wider loop bandwidth compared with phase-locked loop, so it has better jitter performance. In spread-spectrum clock, we replaced external reference signal of sub-sampled phase detector with that signal triggered by voltage-controlled oscillator. The design makes input signals of sub-sampled phase detector, including the signal triggered by voltage-controlled oscillator and differential output of voltage-controlled oscillator, come from voltage-controlled oscillator and lose lock in inherent direction. Therefore, if we carefully adjust the direction and monitor turning points, we can perform smooth triangular wave spread spectrum. The design gets more advantages of chip area, power, EMI reduction and jitter performance because the design has larger loop bandwidth and simple architecture. In addition, we also adopt the current mode capacitor amplification to save more chip area.

    The proposed spread-spectrum clock generator circuit is fabricated in TSMC 40nm 1P9M CMOS process at 6 GHz operating frequency. The supply voltage is 0.9 V. The input reference frequency is 100 MHz. The reduction of electromagnetic interference is 21 dB with the spread-spectrum mechanism modulated by triangular wave. The chip area is 1.11 mm2. The core area is 0.13 mm2.
    Appears in Collections:[電機工程研究所] 博碩士論文

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML46View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明