使用效率與功率提升技術之瓦特級三五族功率放大器設計;Design of Watt-Level Ⅲ-Ⅴ Power Amplifier Using Efficiency and Power Enhancement Techniques

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题名:	使用效率與功率提升技術之瓦特級三五族功率放大器設計;Design of Watt-Level Ⅲ-Ⅴ Power Amplifier Using Efficiency and Power Enhancement Techniques
作者:	費新哲;Fei, Hsin-Che
贡献者:	電機工程學系
关键词:	功率放大器;三五族;預匹配;Power Amplifier;Ⅲ-Ⅴ group;pre-matching
日期:	2020-08-18
上传时间:	2020-09-02 18:29:36 (UTC+8)
出版者:	國立中央大學
摘要:	本論文主要為設計研製收發機前端之功率放大器，包含一個應用於Ku頻段的功率放大器以及三個操作於Ka頻帶的功率放大器。功率放大器是射頻發射系統中的重要元件，其重要性不言而喻。在發射機的前級電路中，調製振盪電路所産生的射頻信號功率很小，需要一系列的放大級獲得足夠的射頻功率以後，才能經由天線輻射出去。因此在發射端必須擁有一個穩定度高，效率高以及輸出飽和功率高的功率放大器。第二章首先使用穏懋0.25 μm GaN製程設計一個應用於衛星通訊頻帶的功率放大器，使用兩級串接架構，第一級增益單元提升電路的整體功率增益，第二級增益單元使用Class-E的輸出負載匹配網路，從而實現較高的功率增進效率。量測時，電流較模擬小三分之一左右，量測得小信號最大增益為13.4 dB，3 dB頻寬為9 GHz~12.3 GHz。在12 GHz時的模擬飽和功率(Psat)為34.5 dBm，最大功率增進效率(PAE)為37.2 %，功率消耗為7.26 W，晶片面積為2.5×2 mm2。在第三章我們討論關於功率放大器穩定度分析以及當電路發生低頻振盪時的除錯方法。本章使用穏懋0.1 μm GaAs(P1010)以及0.15 μm GaAs(P1522)製程分別設計兩個應用於5G(第五代行動通訊)頻帶的功率放大器。採用雙整合功率合成(Binary Power Combine)架構以及T模型匹配網路之功率放大器，量測得最大小訊號增益為8.5 dB，輸入1 dB增益壓縮點(IP1dB)約為16 dBm，輸出1 dB增益壓縮點(OP1dB)約為24 dBm，飽和功率(Psat)為25 dBm，功率消耗為3.11 W，晶片面積為2.5 × 2 mm2。採用中和穩定(Neutralization)架構之功率放大器，其量測得小訊號最大增益為13.6 dB，3 dB頻寬為26.6 GHz~30.6 GHz，模擬得輸出1 dB增益壓縮點(OP1dB)約為24.3 dBm，飽和功率(Psat) 為26.2 dBm，模擬得最大功率增益效率為23 %，功率消耗為1.34 W，晶片面積為2×1 mm2。第四章使用穏懋0.15 μm GaAs(P1555)製程設計一個三級功率放大器，採用了預匹配(Pre-matching)之輸出匹配網路，使用該種輸出匹配方式，可以等效為單段高阻抗傳輸線的匹配，完成由低阻到高阻的阻抗轉換，能夠增加電路的頻寬並降低匹配網路的損耗。每一級放大單元皆串聯一組RC並聯電路來改善穩定度，第一、二級為增益單元以提升電路整體功率增益，第三級為功率輸出單元，採用電晶體兩兩並聯的方式，共合併四顆電晶體，以取得較高的飽和功率。同時加入奇模電阻以防止奇模振盪產生。量測得最大小訊號增益為16.9 dB，3 dB頻寬為24.5 GHz~30.7 GHz。模擬得輸入1 dB增益壓縮點(IP1dB)約為17 dBm，而輸出1 dB增益壓縮點(OP1dB)約為29.2 dBm，飽和功率(Psat)為32.2 dBm，功率消耗為9.81 W，晶片面積為3×2 mm2。最後於第五章總結本篇論文所提出之電路與討論未來研究方向。 ;The purpose of this thesis is to design a power amplifier (PA) for the front-end of transceiver. Including a power amplifier for Ku band and three power amplifiers for Ka band. Power amplifier is an important component in RF system. In the front-end circuit of the transmitter, the RF signal power generated by the modulation is very small, and it needs a series of amplifier stages to obtain sufficient RF power to radiate by antenna. Therefore, it is necessary to have a power amplifier with high stability, high efficiency and high saturation output power in the transmitter system. In Chapter 2, a Ku-band power amplifier using WIN 0.25 μm GaN process for digital satellite broadcasting application is presented. With two-stage topology and Class-E output matching network, the proposed can improve the overall power gain, and achieve high power-added efficiency (PAE). The measurement current is about one third less than the simulation. The small signal peak gain is 13.4 dB at 10.3 GHz, and 3-dB bandwidth from 9 GHz to 12.3 GHz. As the frequency 12 GHz, the simulated saturation output power (Psat) of 34.5 dBm, the peak PAE of 37.2 %. The power consumption is 7.26 W, and the chip size is 2.5×2 mm2. In Chapter 3, the analysis of the stability is presented to solve the low-frequency oscillation. Two Ka-band power amplifiers for 5G (fifth generation mobile communication) application, using WIN 0.1 μm GaAs (P1010) and WIN 0.15 μm GaAs (P1522) processes. The power amplifier is designed using binary power combine and T-model matching network. With a dc power consumption of 3.11 W, the proposed power amplifier features small signal gain of higher than 8.5 dB, 1-dB gain compression point output power of 24 dBm, saturation output power of 25 dBm. The chip size of the power amplifier is 2.5×2 mm2. With the power amplifier of neutralization topology, the measured small signal gain is 13.6 dB, the 3-dB bandwidth from 26.6 GHz to 30.6 GHz. The simulated output power at 1-dB gain compression point is 24.3 dBm, the saturated output power is 26.2 dBm, the peak PAE is 23%. The power consumption is 1.34 W, the chip size is 2×1 mm2. In chapter 4, a Ka-band three-stage power amplifier using pre-matching output network is designed by WIN 0.15 μm GaAs (P1555) process. By using this kind of output matching network can be equivalent to a single high impedance transmission line, the conversion from low impedance to high impedance can increase the 3-dB bandwidth and reduce the loss of the matching network. Each stage series a RC in parallel to improve stability, the first and second stages increase the power gain of the circuit, and the third stage combines four transistors in parallel as the power stage to obtain a higher output power. Odd-mode resistance is also used to prevent odd-mode oscillation. The measured small signal gain is 16.9 dB, the 3-dB bandwidth is from 24.5 GHz to 30.7 GHz. the simulated output 1-dB gain compression point is 29.2 dBm, the saturated output power is 32.2 dBm, the power consumption is 9.81 W, the chip size is 3×2 mm2. Finally, in Chapter 5 we try to summarizes the proposed circuits and discuss the future research direction.
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