| 摘要: | 近年來，隨著製程的演進和發展，高速類比電路的需求是日益增高。例如: 高速的類比數位轉換器(ADC)、數位類比轉換器(DAC)、高解析度影像傳輸設備…等等，而其中高頻寬、高迴轉率的運算放大器就扮演著非常重要的角色。
本論文提出了三種架構，第一種架構是使用GaN製程實現的高功率線性穩壓器，能將100V穩定轉換成5.5V，以提供穩定的電源供應電壓給另外兩種架構。另兩種架構為用於放大高速數位類比轉換器(DAC)之輸出訊號以驅動高負載的類比電路設計，為一高頻寬、高迴轉率、低輸出阻抗的運算放大器。其中架構主要分為兩種: 一是典型的電壓回授互補式雙級放大器(簡稱G1)具迴轉率補償之驅動電路，其開迴路增益可達69dB，單位增益頻寬183M Hz，其靜態功耗可達6.3mW。另一是電流回授之高頻寬、高迴轉率、低輸出阻抗的轉阻放大器(簡稱G2)，其開迴路增益可達50dB，迴轉率在輸出峰對鋒值VPP=2.5V及負載0.9nF//50ohm時為582V/μs，單位增益頻寬363M Hz，其輸出阻抗可達0.1ohm (@10 M Hz)，靜態功耗1.25W。本論文提出之架構以積體電路實現，透過 0.18um CMOS 製程使用，單供應電壓為5.5V，負載阻抗為0.9nF//50ohm，測試訊號頻率在10M Hz時，其總諧波失真(THD)為2.4%。在30M Hz時為8%。
;In recent years, with the evolution and development of manufacturing processes, the demand for high-speed analog circuits is increasing. For example: high-speed analog-to-digital converters (ADC), digital-to-analog converters (DAC), high-resolution image transmission equipment...etc. Among them, high-bandwidth, high-slew rate operational amplifiers play a very important role. This paper proposes three architectures. The first architecture is a high-power linear regulator implemented using a GaN process, which can stably convert 100V to 5.5V to provide a stable power supply voltage to the other two architectures. The other two architectures are analog circuits designed to amplify the output signal of a high-speed digital-to-analog converter (DAC) to drive high loads. They are an operational amplifier with high bandwidth, high slew rate, and low output impedance. The architecture is mainly divided into two types: The first is a typical voltage feedback complementary two-stage amplifier (G1) with slew rate compensation drive circuit, its open loop gain can reach 69dB, unity gain bandwidth 183M Hz, its static power The power consumption can reach 6.3mW. The other is a current feedback transimpedance amplifier (G2) with high bandwidth, high slew rate, and low output impedance. Its open-loop gain can reach 50dB. The slew rate is at the output peak-to-front value VPP=2.5V and load 0.9nF//50ohm is 582V/μs, unity gain bandwidth is 325M Hz, its output impedance can reach 0.1ohm (@10 M Hz), and static power consumption is 1.25W. The architecture proposed in this paper is implemented by an integrated circuit, used through a 0.18um CMOS process, with a single supply voltage of 5.5V, a load impedance of 0.9nF//50ohm, and the total harmonic distortion (THD) when the test signal frequency is 10M Hz. Is 2.4%. 8% at 30M Hz. |
