| 摘要: | Ka 頻段（26.5-40 GHz）是目前第五代行動通訊所應用的頻段，
此頻段的頻寬很大，通常是應用在衛星通訊上，35-GHz的雲雷達也
是毫米波頻段下的應用之一。無論是第五代行動通訊還是雷達系統，
在此頻帶中，相位陣列是不可或缺的角色。相位偏移器是相位陣列中
最為關鍵的電路之一，主要功能是可用來提供一個可調的相位差。若
控制相位陣列中各天線間的相位差，即可改變相位陣列發射與接收的
方向。在本論文中，我們使用兩種製程來實現Ka 頻段的被動式相位
偏移器，分別為TSMC 90-nm CMOS製程與TSMC 0.18-um CMOS製程，並且我們使用TSMC 90-nm CMOS製程實現Ka 頻段的數位式
控制之可變增益放大器。
在第二章中，我們使用TSMC 90-nm CMOS製程設計Ka 頻
段四位元被動式相位偏移器。電路的操作頻率為35 GHz，其中
的22.5°
、45°及90°
相位偏移器都是使用傳輸線基全通網路的架
構。180°相位偏移器則是使用兩級中心頻率不同的傳輸線基全通網路
串接而成，中心頻率分別為25 GHz（LB）及50 GHz（HB）。量測
結果顯示，所有狀態的相位偏移量皆有變大且往高頻頻偏的趨勢，均
方根相位誤差也上升至22.96°
，因此我們重新定義頻寬為Ka 頻段。
在Ka 頻段內，返回損耗皆大於8.51 dB，植入損耗最大上升至20.1 dB，振幅誤差皆在± 1.73以內。
我們為了改善量測結果去做重新模擬，主要採用兩種方法。第一
種是針對實際上傳輸線的電氣長度比預期的短，因此去減少疊構的介
電常數。而第二種是因為無法確認介電常數為主要原因，我們猜測
MIM電容的model上的寄生電感比實際上的少，因此我們在MIM電
容旁邊串聯電感，以確保model與實際上的寄生電感不會相差太多。
而這兩種方法都能讓模擬結果貼近量測結果。
在第三章中，我們使用TSMC 90-nm CMOS製程設計Ka 頻段
90
°相位偏移器，電路的操作頻率為35 GHz，電路架構使用傳輸線基
全通網路。此電路為2.6節提到重新模擬（調低疊構的介電常數）的
電路來進行設計，2.6節中我們調低疊構的介電常數，使傳輸線的電
氣長度能夠與實際做出來的電氣長度一樣。我們將介電常數調低15%後，使相位偏移量能與量測結果貼近，並且我們擷取其中的90°
相移
級來做重新設計，並微調其中的電容值，使相位誤差能夠在3°以內。
量測結果顯示，相位誤差低於3°時的相對頻寬可達28.8%（33.6-44.9）。在頻寬內，返回損耗皆大於12.25 dB，植入損耗皆小於5.09 dB，振幅誤差皆在 ±0.36內。
我們在2.6節推測實際上傳輸線的電氣長度會比預期的短，因此
我們調低疊構的介電常數做重新模擬。但我們無法確認介電常數為主
要原因，因此我們在重新設計電路時，有搭配傳輸線測試鍵去做下
線。而傳輸線的模擬結果與量測結果顯示，量測時的電氣長度確實會
比模擬時來的短，因此可以驗證2.6節的推論是正確的。
在第四章中，我們使用TSMC 0.18-um CMOS製程來實現第三
章使用TSMC 90-nm CMOS製程的電路。雖然使用TSMC 0.18-um CMOS製程在35-GHz時的性能會比較差，但在成本考量上使用TSMC 0.18-um CMOS製程的成本可以比較低。而此電路為先前實驗室學長的電路[25]使用傳輸線基全通網路之數位式四位元相位偏移器，這個電路可以看到量測結果與模擬結果相差很多，因此我們擷取這個電路的甹田
相移級做重新模擬，使模擬結果能夠貼近量測結果。
接著我們推論導致相位偏移量頻偏且變小的原因可能是因為
TSMC 0.18-um CMOS製程原本提供MIM電容的model的寄生電感
估的比實際上來的大，因此我們在MIM電容旁邊串聯負的理想電
感，將MIM電容的寄生電感扣回來。加上電感使相位偏移量與量測
結果貼近後，我們將90°相移級做重新設計，微調電容值使相位誤差
能夠在3°以內。而量測結果顯示，相位誤差低於3°時的相對頻寬可達
22.58%（33-41.4 GHz）。在頻寬內返回損耗皆大於13.9 dB，植入損
耗皆小於5.9 dB，振幅誤差皆在 ±0.44 dB內。
我們在4.2節推測實際上傳輸線的電氣長度會比預期的短，因此
我們調低疊構的介電常數做重新模擬。但我們無法確認4.2節的推論
是否為原因之一，因此我們在重新設計電路時，有搭配兩條長度不一
樣的傳輸線測試鍵去做下線。傳輸線的模擬結果與量測結果顯示，量
測時的電氣長度確實會比模擬時來的短，因此可以驗證4.2節電氣長
度的推論是正確的。
相位陣列中最重要的電路是相位偏移器，可用於調控各element訊號的相位差，進而調制天線陣列的波束方向。然而，由天線陣列的理論可知，若可調控各element訊號的振幅，使天線陣列變為non-uniformly excited，則可用來調整波束的side-lobe level。在第五章中，我們使用TSMC 90-nm CMOS製程設計35-GHz數位式控制之可變增益放大器，電路核心部分是由五路全差動式疊接並聯而成，
輸入端與輸出端是使用變壓器來做匹配。量測結果顯示，S 參數皆有
往低頻頻偏的趨勢，全開狀態下的輸入返回損耗從34.7 GHz頻偏至29.6 GHz，輸出返回損耗從34.9 GHz頻偏至30.6 GHz。全開狀態下的增益從13.9 dB降到至10.3 dB，峰值也從34.4 GHz頻偏至29.8 GHz；在29.8 GHz下，所有狀態的輸入返回損耗皆大於9.1 dB，所有狀態的輸出返回損耗皆大於5.7 dB，所有狀態中增益最高可達10.3 dB，由於第8個狀態的增益小於0 dB，因此增益可調範圍為10.3 dB。所有狀態中最大的相位變化量從1.5°
上升至20
°。
因為量測結果的輸出返回損耗明顯比模擬結果差，因此我們將輸
出端的變壓器做重新模擬。在重新模擬中，我們先將電路模擬未考慮
到的電晶體走線考慮進去，並且推測輸出端變壓器的電容可能會因為
製程變異導致M8層與M9層之間的厚度變小。我們將電路中的Cp,D做重新模擬，把M8層與M9層之間的厚度減少40%使容值變好，藉此改善輸出匹配。雖然減少M8層與M9層中間的厚度可以使S 參數頻偏到量測結果的頻率，但增益卻無法降到跟量測結果一樣。接著我們推測可能是變壓器在模擬時的Q 值太高，因此我們在變壓器旁邊並聯1200 Ω的電阻，使變壓器的Q 值降低。在並聯電阻後增益有降低且可以與量測結果貼近。
在本論文中，我們成功實現了Ka 頻段的數位式相位偏移器與可變增益放大器。雖然量測結果與模擬結果相差甚多，但經過重新模擬，我們可以知道此製程在Ka 頻段會有哪些影響，考慮完這些影響後，能夠使結果更加接近我們期望的效能。
;Ka band (26.5--40 GHz) is currently the frequency band used by the fifth generation of mobile communications. This frequency band has a large bandwidth and is usually used in satellite communications. The 35-GHz cloud radar is also one of the applications in the millimeter wave frequency band. Whether it is the fifth-generation mobile communications or radar systems, phased arrays are an indispensable character in this frequency band. The phase shifter is one of the most critical circuits in the phase array, and the main function can be used to provide an adjustable phase difference. If the phase difference between the antennas in the phased array is controlled, the direction of transmitting and receiving in the phased array can be changed. In this thesis, we use two processes to achieve Ka-band passive phase shifters, namely TSMC 90-nm CMOS process and TSMC 0.18 um CMOS process, and we use TSMC 90-nm CMOS process to achieve a 35-GHz digitally controlled variable gain amplifier.
In Chapter 2, we use the TSMC 90-nm CMOS process to design a Ka-band 4-bit passive phase shifter. The operating frequency of the circuit is 35 GHz. The 22.5°, 45° and 90° phase shifter use transmission line-based all-pass network architecture, and the 180° phase shifter uses two stages of transmission line-based all-pass network with different center frequencies. The network is connected in series, and the center frequencies are 25 GHz (LB) and 50 GHz (HB). The measurement results show that the phase shift of all states tends to increase and shift to high frequency, and the root mean square phase error also rises to 22.96°. Therefore, we redefine the bandwidth as the Ka band. In the Ka band, the return loss is greater than 8.51 dB, the insertion loss rises to 20.1 dB, and the amplitude error is within ± 1.73 dB.
In order to improve the measurement results to resimulate, we mainly use two methods. The first is for electrical length of the actual transmission line that is shorter than expected, so we reduce the dielectric constant of the stack. Using the second method because We can′t confirm the dielectric constant as the main reason.
We guess that the parasitic inductance on the MIM capacitor model is less than the actual one. Therefore, we series inductor next to the MIM capacitor to make sure that the parasitic inductance of the model is not too different from the actual parasitic inductance. Both of methods can make the simulation results close to the measurement results.
In Chapter 3, we use TSMC 90-nm CMOS process to design a Ka-band 90°
phase shifter. The operating frequency of the circuit is 35 GHz and the circuit architecture uses a transmission line-based all-pass network. We design the circuit which is mentioned in section 2.6 to resimulate (turn down the dielectric constant of the stack). In section 2.6, we turn down the dielectric constant of the stack so that the electrical length of the transmission line can be close to the actual electrical length. We turn down the dielectric constant by 15% to make the phase shift close to the measurement result, and we capture the 90°
phase shifter to redesign it. We fine-tune the capacitance value so that the phase error can be Within 3°
. The measurement results show that when the phase error is less than 3°
, the relative bandwidth can reach 28.8% (33.6-44.9 GHz). Within the bandwidth, the return loss is greater than 12.25 dB, the insertion loss is less than 5.09 dB, and the amplitude error is within ±0.36 dB.
We guess in Section 2.6 that the actual electrical length of the transmission line will be shorter than expected, so we turn down the dielectric constant of the stack for resimulation. But we can′t confirm that the dielectric constant is the main reason. Therefore, when we redesign the circuit, we will design the transmission line test key. The simulation results and measurement results of the transmission line show that the electrical length of the measurement result will be shorter than the electrical length of the simulation result, so it can be verified that the inference in section 2.6 is correct.
In Chapter 4, we use TSMC 0.18 um CMOS process to realize the circuit that uses the TSMC 90-nm CMOS process in Chapter 3.Although the performance of using TSMC 0.18 um CMOS process at 35-GHz will be poor, the cost of using TSMC 0.18 um CMOS process can be relatively low.The circuit of the former laboratory master [25] is digital 4-bit phase shifter using transmission line-based all-pass network. We can see that the measurement result is very different from the simulation result in this circuit, so we capture the 90° phase shifter of this circuit and resimulated it to make the simulation result close to the measurement result.
Then we guess that the reason for the phase shift has a tendency to become smaller and shift to high frequency. It may be that the parasitic inductance of the MIM capacitor model originally provided by the T18 process is estimated to be larger than the actual one. Therefore, we series a negative ideal inductance next to the MIM capacitor to make the parasitic inductance of the MIM capacitor buckle back. After we add the inductance to make the phase shift close to the measurement result, we redesign the 90° phase shifter, we fine-tune the capacitance value so that the phase error can be Within 3°. The measurement results show that when the phase error is less than 3°, the relative bandwidth can reach 22.58% (33-41.4 GHz). Within the bandwidth, the return loss is greater than 13.9 dB, the insertion loss is less than 5.9 dB, and the amplitude error is within ±0.44 dB.
We guess in Section 4.2 that the actual electrical length of the transmission line will be shorter than expected, so we turn down the dielectric constant of the stack for resimulation. But we can′t confirm whether the inference in Section 4.2 is one of the reasons. Therefore, when we redesign the circuit, we will design two transmission line test keys. The simulation results and measurement results of the transmission line show that the electrical length of the measurement is shorter than that of the simulation. Therefore, it can be verified that the inference in section 4.2 electrical length is correct.
The most important circuit in the phase array is the phase shifter, which can be used to adjust the phase difference of each element signal, and then modulate the beam direction of the antenna array. However, it can be known from the theory of antenna arrays that if the amplitude of each element signal can be adjusted to make the antenna array non-uniformly excited, it can be used to adjust the side-lobe level of the beam. In chapter 5, we use TSMC 90-nm CMOS process to design a 35-GHz digitally controlled variable gain amplifier. The core part of the circuit is composed of five fully differential cascode stages in parallel. Input and output transformer are used for matching. The measurement results show that the S-parameters have a tendency toward low frequency deviation. The input return loss in fully open state shifts from 34.7 GHz to 29.6 GHz, the output return in fully open state loss shifts from 34.9 GHz to 30.6 GHz, and the gain in fully open state reduces from 13.9 dB to 10.3 dB. The peak value also shifts from 34.4 GHz to 29.8 GHz; at 29.8 GHz, the input return loss in all states is greater than 9.1 dB, the output return loss in all states is greater than 5.7 dB, and the gain in all states is up to 10.3 dB. The gain of 8 states is less than 0 dB, so the adjustable range of gain is 10.3 dB. The maximum phase shift in all states increases from 4.5± to 20±.
Because the output return loss of the measurement result is significantly worse than the simulation result, we resimulate the output transformer. In the resimulation, we consider the transistor lines that are not considered in the circuit simulation, and speculate that the capacitance of the output transformer might be caused by process variations to reduce the thickness between the M8 layer and the M9 layer. We resimulate the Cp,D in the circuit, and reduce the thickness between the M8 layer and the M9 layer by 40% to make the capacitance value better, thereby improving the output matching. Although reducing the thickness between the M8 layer and the M9 layer can make the S parameter′s frequency shift to the frequency of the measurement result, the gain can′t be reduced to the same as the measurement result. Then we speculate that the value of Q of the transformer in the simulation is too high, so we connecte a resistor of 1200 Ω in parallel next to the transformer to reduce the value of Q of the transformer. After we connect the resistors in parallel, the gain is reduced and can be close to the measurement result.
In this paper, we have successfully implemented a digital phase shifter and variable gain amplifier in the Ka band. Although the measurement results are quite different from the simulation results, after resimulating, we can know what effects the process will have in the Ka band. After considering these effects, the results can be closer to our expected performance. |
