| 摘要: | 隨著人口結構逐漸老化，老年及長照人口的即時醫療監控需求越來越高，因此近年來穿戴式裝置興起，市面上出現越來越多可攜式生醫電子產品。此外，近年來養生與健身風氣的盛行，一般民眾對於了解自身生理狀況也越來越重視，對於量測並分析自身心跳、血壓與血氧等數據的需求也逐漸增高。人體的生理訊號一般而言都極其微小，且各種生理訊號的頻寬不盡相同，如何在不受雜訊影響下，放大與分析生理訊號在生醫感測系統中極其重要。綜合以上因素，本電路以低功耗、低成本、易整合為設計的目標。
本論文實現一應用於生醫訊號感測之類比數位轉換器(Analog-to-digital converter, ADC)，此類比數位轉換器使用非同步時脈(Asynchronous clock)連續漸進式架構(Successive-approximation, SAR)來增加前端類比電路(Analog fount-end, AFE)追蹤時間並且提高全差動輸入以利提升整體系統的訊號雜訊比。在低頻寬(10 MHz以下)與中等解析度(10 ~ 14 bits)的應用中，連續漸進類比數位轉換器在功率消耗方面優於積分三角類比數位轉換器(Sigma Delta ADC)。使用非同步時脈可以在較寬的取樣頻率範圍內，實現一致的性能與較低的功率消耗。其可調取樣頻率範圍可應用於腦波訊號(Electroencephalography, EEG)、心電訊號(Electrocardiography, ECG)及眼電訊號(Electrooculogram, EOG)等生理訊號檢測。使用內置時脈產生器的架構與傳統應用於高速連續漸進式類比數位轉換器的延遲線架構相比，內置時脈產生器可以在較低的頻率下操作。全差動輸入可以抵消前端類比電路的直流偏移，降低製程、電壓與溫度對系統的影響。
本論文採用TSMC 0.18 um CMOS標準製程，晶片面積0.680 mm2 (含ESD I/O PAD)，電源電壓1.2 V，通常取樣率400sps，最高取樣率可達10ksps。輸入電壓範圍300mV ~ 900mV，11位元解析度。當取樣頻率為10ksps時，整體電路功耗為1.7 µW，核心電路功耗為932 nW。
;With the gradual aging of the population structure, there is an increasing demand for real-time medical monitoring of the elderly and long-term care groups. Consequently, more and more portable biomedical electronic products have come out. In recent years, the trend of health preservation and fitness has become more and more important for the public to understand their physical condition. The demand for the measurement and analysis of heartbeat, blood pressure, blood oxygen and other data is gradually increasing. Since the physiological signals of the human body are generally very small, and the bandwidths of various physiological signals are not the same, how to fully amplify and analyze the signals without being affected by noise is the main requirement of the biomedical sensor system. Therefore, the circuit design aims at low power consumption, low cost, and easy integration.
This thesis presents an implementation of a fully differential asynchronous successive-approximation analog-to-digital converter (SAR ADC) applied to biomedical signal sensing. By increasing the analog front-end circuit tracing time and fully differential input, improving the signal-to-noise ratio of the entire system is achieved. In applications with low bandwidth (less than 10 MHz) and medium resolution (10 to 14 bits), the SAR ADC is superior to the Sigma-Delta ADC in terms of power consumption. Using asynchronous clocks can achieve consistent performance and lower power consumption within a wide range of sampling frequencies. Its adjustable sampling frequency can be applied to the detection of physiological signals such as electroencephalogram (EEG), electrocardiogram (ECG) and electrooculogram (EOG). Compared with the conventional delay line architecture used in the high-speed SAR ADC, the architecture using the internal clock generator can operate at low frequency. The fully differential input can cancel DC offset of the front-end analog circuit and reduce variation of process, voltage and temperature on the system.
This work used TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM FSG Al 1P6M 1.8&3.3 V process, the chip area is 0.680 mm2 (including ESD I/O PAD), supply voltage is 1.2 V. Input voltage range is 300 mV ~ 900 mV, 11-bit resolution, typical sampling rate is 400 S/s, and highest sampling rate is 10 kS/s. When the sampling frequency is 10 kS/s, whole chip power consumption is 1.7 µW, and the core circuit power consumption is 932 nW. |
