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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8948


    Title: 低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作
    Authors: 邱瑞德;Ran-De Cho
    Contributors: 電機工程研究所
    Keywords: 低雜訊;輸出緩衝器;時脈回復器;同時性邏輯轉換雜訊;usb2;output buffer;clock recovery;Simultaneous Switching Noise
    Date: 2000-06-16
    Issue Date: 2009-09-22 11:38:11 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 高速I/O是決定電子裝置間能否成功傳送資料的一個重要因素。這篇論文主要討論了兩個相關I/O的主題。首先討論有關同時性邏輯轉換雜訊(Simultaneous Switching Noise),是高速數位電路中最主要的雜訊之一。我們先對同時性邏輯轉換雜訊做一概略性的介紹。接下來提出一個不但可以降低同時性邏輯轉換雜訊與電路輸出振盪問題而且還能維持驅動能力的低雜訊輸出緩衝器。並以UMC 0.35um 1P5M的數位製程,來實際驗證理論分析及輸出級電路設計技巧。經由晶片量測的結果,我們在電路輸出震盪及同時性邏輯轉換雜訊上可以分別降低60%及70%。另外,我們也提出了一套特性化流程來估算SSO(Simultaneous Switching Outputs)所需的電源/接地對的個數及其所額外增加的延遲時間。 其次我們提出一個新的全數位式時脈回復器的架構,並利用USB2的高速規格(480Mb/s)來驗證。USB2為一個新的電腦週邊萬用匯流排的規格,而USB2中的實體層製作主要包涵了接發端和時脈回復器,製作一個全數位式、低功率損耗和小面積時脈回復器是USB2中相當重要的一環。而我們除了提出這個時脈回復器之外,同時也提出了整個USB2實體層的製作架構。 High speed I/O is the key component to successfully transmit data between electronic devices. There are two research topics in this thesis. First we focus on the overview of simultaneous switching noise (SSN). We will propose an output buffer for reducing SSN, output signal ringing and maintain DC current capability. Also we provide a program to estimate power pads for SSO. Second, a clock recovery architecture and circuit is proposed for Universal Serial Bus 2 (USB2) high-speed mode (480M bits per second). USB2 is a new serial bus standard for the peripheral of PC today. The physical layer of USB2 consists of a transceiver and the clock recovery (CR). For USB2 high-speed 480M bits per second, it is important to design an all digital, low power, small area clock recovery. In this thesis, we propose an overall architecture of USB2 physical layer. We also propose a new all digital clock recovery for USB2 physical layer. However, it consume only when working at 480M bit per second.
    Appears in Collections:[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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