適用於合成孔徑雷達之測距都普勒演算法即時成像硬體實作與系統整合;Hardware Implementation of Range Doppler Algorithm for Synthetic Aperture Radar Real Time Imaging and System Integration

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题名:	適用於合成孔徑雷達之測距都普勒演算法即時成像硬體實作與系統整合;Hardware Implementation of Range Doppler Algorithm for Synthetic Aperture Radar Real Time Imaging and System Integration
作者:	林家兆;Lin, Jia-Zhao
贡献者:	電機工程學系
关键词:	合成孔徑雷達;測距都普勒演算法;及時成像;Synthetic Aperture Radar;Range Doppler Algorithm;Real Time Imaging
日期:	2022-08-17
上传时间:	2022-10-04 12:07:17 (UTC+8)
出版者:	國立中央大學
摘要:	合成孔徑雷達成像能夠不受天氣影響的進行成像，而即時成像可使其應用價值大幅上升，也可降低最終圖像資料的傳輸量，然而大點數的即時成像需面臨大量資料傳輸與處理的問題，且需要高速的運算。我們選擇使用測距都普勒演算法來完成整個成像的運算，對於測距都普勒演算法而言，二維的快速傅立葉轉換需要花費整個計算80%以上的計算時間，為了能夠達成即時成像的需求，如何使其他部分的計算能夠配合快速傅立葉轉換的資料流向便即為重要。而整個測距都普勒演算法除了二維的快速傅立葉轉換外，主要還包含了測距方向壓縮、二次測距方向壓縮、測距偏移修正及方位方向壓縮等四個步驟。為了能夠達到即時成像，此研究的重點會放在對各個步驟的間的資料傳遞與處理，並藉由共用運算資源與排程來減少整個硬體資源的消耗，而利用管線化設計提高計算速度，並將所需之各種參數在適當的時間平行計算，也可有效減少快速傅立葉轉換以外的計算時間。而資料流經過快速傅立葉轉換後的位元序列反轉，以及因都普勒效應造成之頻率偏移，皆是整個系統所需處理的問題。整個系統會涵蓋至與電腦端的資料交換部分，而此論文主要內容包含測距都普勒演算法部分之硬體與二維快速傅立葉轉換運算之整合，而此硬體包含3種可供選擇的成像大小，包含測距方向為8192、16384、32768點的情況，而方位方向則固定為8192點，此外整個系統的操作頻率為100MHz，內含雙精確度、客製化浮點數及定點數，依不同計算精度要求使用相應之數值計算，藉此提高操作頻率並維持成像的品質，考慮到後續的資料傳輸問題，我們使用的Xilinx開發板Virtex UltraScale+ HBM VCU128 FPGA在資料傳輸上具有HBM可供使用，透過多個AXI port來滿足成像加速器即時處理所需要50Gbps的存取速度，最終最大尺寸8K×32K圖像的完整成像時間約為1.36秒，而預估的資料獲取時間約為1.6秒，滿足了即時成像的要求。;Synthetic Aperture Radar imaging can actively perform imaging without being affected by weather, and real-time imaging can greatly increase its application value and reduce the transmission volume of raw echo signals. However, real-time processing with large image sizes needs an efficient architecture for high-speed operations. In this thesis, range Doppler algorithm is implemented to complete the entire imaging operation. For range Doppler algorithm, the two-dimensional fast Fourier transform consumes more than 80% computation time. In order to meet the requirements of real-time imaging, it is important to arrange the data flow of the remaining modules to match with the data flow of the two-dimensional fast Fourier transform. In addition, the entire range Doppler algorithm includes four steps: range compression, secondary range compression, range cell migration correction and azimuth compression. This research focuses on the data transfer and processing among these steps, reducing hardware resources by scheduling as well as hardware sharing, and improving the operating frequency by using pipelines. With well-scheduled parameter calculation, the streaming input and output of SAR signals can be satisfied. This hardware supports three range FFT sizes, including 8192, 16384, and 32768, and the azimuth FFT size is fixed at 8192. The operation frequency is 100MHz. The datapaths contain three different precisions, double precision, customized floating-point and fixed-point representation to tradeoff performance and complexity. The Xilinx Evaluation board Virtex UltraScale+ HBM VCU128 FPGA is used. Multiple AXI ports are connected to offer the data transfer rate of about 50Gbps. Finally, the processing time of a 8K×32K image is 1.36s, and the echo signal acquiring time is 1.6s. The goal of real-time processing is achieved.
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