應用於Sub-6 GHz n79 頻段互補式金氧半導體 F23 類壓控振盪器與使用動態偏壓B/C類混合式壓控振盪器暨整數型鎖相迴路之研製;Implementations on CMOS Sub-6 GHz n79 band Class-F23 Voltage Control Oscillator, Dynamic Biasing Class-B/C Hybrid-Mode Voltage Controlled Oscillator, and Integer-N Phase Locked Loop

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題名:	應用於Sub-6 GHz n79 頻段互補式金氧半導體 F23 類壓控振盪器與使用動態偏壓B/C類混合式壓控振盪器暨整數型鎖相迴路之研製;Implementations on CMOS Sub-6 GHz n79 band Class-F23 Voltage Control Oscillator, Dynamic Biasing Class-B/C Hybrid-Mode Voltage Controlled Oscillator, and Integer-N Phase Locked Loop
作者:	賴柏儒;Lai, Po-Ju
貢獻者:	電機工程學系
關鍵詞:	互補式金屬氧化物半導體;B/C類;F類;壓控振盪器;鎖相迴路;動態偏壓;CMOS;Class-B/C;Class-F;Voltage-Controlled Oscillator (VCO);Phase Locked Loop(PLL);Dynamic Biasing
日期:	2022-08-26
上傳時間:	2022-10-04 12:10:05 (UTC+8)
出版者:	國立中央大學
摘要:	本論文擬研究射頻收發機中之本地振盪源相關電路，研製應用於第五代行動通訊(5th generation wireless systems)之n79頻段本地振盪電路。本論文首先介紹相位雜訊與LC振盪器中用以分析相位雜訊的模型以及介紹何謂flicker noise upconversion，接著介紹尾濾波與二次諧波共振技術，最後介紹所實現之電路。本論文一共實現三種電路，皆使用tsmcTM 0.18 μm互補式金氧半導體製程製作，內容如下所述： I.低相位雜訊n79頻段F23類壓控振盪器本電路實作具有低相位雜訊特性之F23類壓控振盪器，使用變壓器耦合實作F23類共振腔，並獨立主、副線圈中心抽頭偏壓以優化直流功耗。整體電路經由量測後，可調頻率為4.39 ~ 5.04 GHz (13.8 %)，電路功耗為5.64 ~ 7.01 mW，相位雜訊在 1-MHz 偏移頻率下最低為−122.56 dBc/Hz，對應 FoM最高為−187.15 dBc/Hz，整體晶片面積包含I/O PAD為1.1 × 1 mm2。 II.使用動態偏壓低雜訊低功耗B/C類混合式壓控振盪器本電路實作具有低功耗、低相位雜訊特性之B/C類混合式壓控振盪器，C類振盪器具有低功耗、高電流效率以及低相位雜訊之特性，並且提出使用動態偏壓以及操作在B類的PMOS輔助振盪，使振盪器可以穩定起振。整體電路經由量測後，可調頻率為4.42 ~ 5.07 GHz (13.63 %)，電路功耗為3.44 ~ 3.54 mW，相位雜訊在 1-MHz 偏移頻率下最低為−119.09 dBc/Hz，對應 FoM最高為−186.55 dBc/Hz，整體晶片面積包含I/O PAD為0.98 × 0.86 mm2。 III.利用B/C類混合壓控振盪器之n79頻段整數型鎖相迴路本電路包含使用動態偏壓的B/C類混合式壓控振盪器、電流模式邏輯除頻器、雙轉單緩衝放大器、真單一相位時脈除頻器、全擺幅緩衝器、相位頻率比較器、電荷幫浦以及迴路濾波器，利用上述電路合成一個鎖相迴路，並於章節中完整分析各子電路之用途及數學分析。整體電路經由量測後，當輸入參考頻率為35 MHz到38.125 MHz時輸出頻率能成功鎖定在4.48 GHz到4.88 GHz，除數設計為128，整體鎖相迴路功耗為25.66 mW，在中心頻4.7 GHz時量測後參考突波大小為-47.26 dBc，鎖定後相位雜訊在1 MHz偏移時為-99.31 dBc/Hz，整體晶片面積包含I/O PAD為1.26 × 0.97 mm2。 ;This thesis aims to design local oscillator (LO) circuits for the signal source of the fifth generation (5G) cellular communications in n79 band transceivers. In this thesis, we firstly introduce the phase noise and LC oscillator models used to analyze phase noise and what is flicker noise upconversion, then explain the tail filter and second harmonic resonance topology, and finally illustrate the circuit implemented in this thesis. In this thesis, three LO circuits were implemented in tsmcTM 0.18 μm CMOS processes. The developed LO circuits are listed as follow, I.A low phase noise n79-band Class-F23 VCO Class-F23 oscillator features the low phase noise. In this work, we use transformer coupling technique to realize Class-F23 LC-tank, and separate the center tape of the primary and secondary coils to optimize the DC power consumption. The measurements are listed as below, the operation frequency is from 4.39 to 5.04 GHz (i.e., 13.8% tuning range), and the power consumption is from 5.64 to 7.01 mW. The lowest phase noise at 1-MHz offset frequency is −122.56 dBc/Hz which is correspondent to the FoM of −187.15 dBc/Hz. The chip size included pads is 1.1× 1 mm2. II.A dynamic biasing low phase noise and low power consumption on Class-B/C Hybrid-Mode VCO The Class-C oscillator has the features of low power consumption, high current efficiency and low phase noise. In this work, we proposed a dynamic bias circuit and PMOS auxiliary oscillation operating in Class-B to solve hard start-up problem of the Class-C oscillator. The measurements are listed as below, the operation frequency is from 4.42 to 5.07 GHz (i.e., 13.63% tuning range), and the power consumption is from 3.44 to 3.54 mW. The lowest phase noise at 1-MHz offset frequency is −119.09 dBc/Hz which is correspondent to the FoM of −186.55 dBc/Hz. The chip size included pads is 0.98× 0.86 mm2. III.An integer-N Phase Locked Loop (PLL) with Class-B/C Hybrid-Mode VCO The functional circuit blocks of the designed PLL include a dynamic biasing Class-B/C Hybrid-Mode voltage controlled oscillator, a current mode logic divider, a differential to single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. This thesis analyzes the behavior model of the PLL. The measurements are listed as, the PLL is locked from 4.48 to 4.88 GHz when reference signal is 35 to 38.125 MHz. The division ratio is 128 and the total power consumption is 25.66 mW. At the center frequency of 4.7 GHz, the reference spur is as low as -47.26 dBc and phase noise is -99.31 dBc/Hz at 1-MHz offset. The chip size included pads is 1.26 × 0.97 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

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