| 摘要: | 本論文主要研究微波及毫米波瓦特級切換器及X頻段鎖相迴路。切換器為無線射頻收發機系統中重要的電路，隨著第五代通訊的到來，無線通訊頻率的提升使傳輸損耗也跟著加大。現階段功率放大器已成為熱門的研究項目，但是鮮有瓦特級的高功率切換器以承接功率放大器與天線，因此本論文第二及三章主要研究功率提升之切換器。同時第五代通訊的高頻寬且高速資料傳輸等優勢也顯現出來，其中本地振盪源作為系統中升降頻的角色十分重要，因此本論文第四章主要研究低功耗、低相位雜訊之四相位鎖相迴路。
第一章為論文的緒論。第二章為使用穩懋0.15 μm GaAs-PIN二極體製程，實作共計6顆5及28 GHz的單刀單擲與單刀雙擲串並式切換器與4顆28 GHz的四分之波長並式切換器。由於隨著輸入功率的提升，會導致二極體導通造成插入損耗的提升，因此提出反接串聯架構，利用其反接的特性有效抑制二極體的導通，從而提升切換器的功率乘載能力。同時由於三五族製程背向通口的寄生電感，本章提出電容共振架構以消除其寄生效應，使切換器的隔離度在不影響其他切換器性能的情況下有效的提升。本章比較多種提出的切換器架構與傳統架構，並成功實現輸入1 dB壓縮點大於35 dBm、插入損耗小於1 dB且隔離度大於27.4 dB的高功率低損耗高隔離度切換器。
第三章為行波切換器的設計，利用被動元件等效成傳輸線以縮小面積並保留其傳輸線的特性，達到高頻寬低損耗之特性。本章使用台積電0.18 μm CMOS、穩懋0.15 μm GaN和穩懋0.15 μm GaAs-PIN二極體製程，實作共計12顆各種架構之行波切換器做比較，分別為傳統架構、二極體連接行式、閘極至源極和汲極二極體、反接串聯二極體、電容共振及反接串聯二極體電容共振之切換器。比較多種提出的行波切換器架構與傳統架構，並成功實現輸入1 dB壓縮點大於35 dBm、損耗小於1.7 dB且隔離度大於18.8 dB的高功率切換器。
第四章為X頻段四相位鎖相迴路，使用台積電0.18 μm CMOS設計並實現。鎖相迴路包含變壓器耦合壓控振盪器、相位頻率偵測器、電荷幫浦、迴路濾波器、兩級電流模式除頻器及四級單相位時序除頻器。由於此電路有迴路振盪之現象，需透過外接濾波器使其成功鎖定頻率。變壓器耦合壓控振盪器可調頻率範圍為9.33 GHz至10.1 GHz，輸出功率約為-4 dBm，而鎖相迴路鎖定頻率範圍為9.44 GHz至9.48 GHz，相位雜訊在1 MHz頻率偏移時為-105.1 dBc/Hz，電路直流總功耗為39.8 mW。
最後於第五章總結本篇論文所提出之電路與未來研究方向。
;This thesis mainly studies microwave and millimeter-wave watt-level switches and an X-band quadrature phase-locked loop (QPLL). The Switches are an important part of the wireless radio frequency (RF) transceiver system. Due to the fifth-generation dynamic communication (5G), the frequency is getting higher, and the greater transmission loss. Power Amplifiers (PA) have become popular research at this stage, but there are few watt-level high-power switches to undertake power amplifiers and antennas. Chapter two and chapter three of this thesis focus on boosting the power-handling of the switches. At the same time, the advantages including wide band and high-speed of the fifth-generation dynamic communication have also emerged. Among them, the local oscillator (LO) is very important as the role of upconvert and downconvert in the system. Chapter four focuses on the low power consumption and low phase noise quadrature phase-locked loop.
The first chapter is the introduction of the thesis. In chapter two, six chips of 5 and 28 GHz single-pole single-throw (SPST) and single-pole double-throw (SPDT) switches series-shunt switches and four chips of 1/4λ transmission line shunt switches using 0.15-μm GaAs-PIN diode process provided by WIN Semiconductors corporation. As the input signal power increase, the diodes will be turned on and the insertion loss will also increase. This thesis proposes the Anti-Series diode structure, to suppress the diode conduction by the Anti-diode feature. Thereby improving the power handling of the switches. Due to the parasitic inductance of the back-via in GaAs, this chapter proposes the resonance-capacitance structure to eliminate this parasitic effect. The isolation of the switches can be improved without affecting the other performance of the switches. This chapter compares various proposed structure switches with conventional switches and successfully implements high-power low-loss high-isolation switches. With insertion loss less than 1 dB, IP1dB greater than 35 dBm, and isolation greater than 27.4 dB.
The third chapter is the design of traveling-wave switches, which uses passive components to be equivalent to the transmission line. To reduce the area and retain the characteristics of transmission lines, and achieve the characteristics of high-frequency bandwidth and low insertion loss. This chapter uses TSMC 0.18 μm CMOS, WIN 0.15 μm GaN, and WIN 0.15 μm GaAs PIN-diode processes to implement a total of 12 traveling-wave switches of various structures for comparison. The switch structures include conventional, drain-gate diode-connection, drain-source diode-connection, anti-series diode, resonance-capacitance, and resonance-capacitance anti-series diode. Compare with conventional and various proposed structures of traveling-wave switches, and successfully implements high-power switches. With insertion loss less than 1.7 dB, IP1dB greater than 35 dBm, and isolation greater than 18.8 dB.
In chapter four, design of an X-band quadrature phase-locked loop using TSMC 0.18 μm CMOS. The phase-locked loop includes a transformer-coupled voltage-controlled oscillator (VCO), a phase and frequency detector (PFD), a charge pump (CP), a loop low-pass filter (LPF), two-stage of current mode logic (CML), and four-stage of true single-phase clocking divider (TSPC). Due to the loop being unstable, an external filter is required. The transformer-coupled voltage-controlled oscillator covered from 9.33 GHz to 10.1 GHz, output power has -4 dBm. The quadrature phase-locked loop covered from 9.44 GHz to 9.48 GHz, achieving -105.1 dBc-Hz phase noise at 1 MHz, and the power consumption is 39.8 mW.
In the final chapter, conclusions and future works are presented. |
