時脈產生器設計的考量項目圍繞在效能、功耗與面積上。使用LC振盪器的時脈產生器具有良好的相位雜訊表現，但需要較大的面積，而使用環型振盪器的時脈產生器其相位雜訊表現較差，但所需的面積較少。本論文欲達到擁有較小的面積的目標，故採用環型振盪器做為鎖相迴路的高頻時脈來源。為了抑制環型振盪器的相位雜訊，將透過加大頻寬來改善其表現。 傳統的鎖相迴路在加大頻寬的同時也意味著頻寬內相位雜訊的增加，所以加大頻寬對整體的相位雜訊改善有限。而次取樣鎖相迴路藉由次取樣技巧降低頻寬內的相位雜訊，因此加大頻寬對整體的相位雜訊改善較大。 本論文提出一個使用調整次取樣相位偵測器與充電幫浦的增益，藉此改變頻寬的次取樣鎖相迴路，透過調整增益得到抖動、相位雜訊與參考突波的最佳值。使用TSMC 90 nm 1P9M之CMOS製程實現，電路操作電壓為1 V，輸出頻率為2.4 GHz，功率消耗為3.05 mW。在次取樣充電幫浦增益最大的狀況下，方均根抖動為2.39 ps，相位雜訊在1 MHz的位置為 -103.9 dBc/Hz，晶片面積為0.80 mm2，其中核心電路面積為0.018 mm2。 ;The design of clock generator is focus on its performance, power consumption, and area. The oscillator is the high frequency clock source of the phase-locked-loop (PLL), which dominate the performance. The LC tank oscillator have better phase noise than the ring oscillator but its area large too. The thesis adopts the ring oscillator-based PLL to achieve the aim of small area. Increasing the bandwidth so as to suppress the phase noise of the ring oscillator. The typical PLL extend its bandwidth means increase its in-band noise too. As the results, extend the bandwidth of the typical PLL is minuscule to suppress the phase noise overall. However, the sub-sampling PLL have decrease its in-band noise by sub-sampling technique. Thus, extend the bandwidth of sub-sampling PLL (SSPLL) have improve the performance of phase noise. The thesis implements a SSPLL that achieves the bandwidth change by adjusting the gain of the sub-sampling phase detector and charge pump. By adjusting the gain, the optimal value of jitter, phase noise and reference spur can be tradeoff. The chip implemented by TSMC 90 nm 1P9M CMOS process. The supply voltage is 1V of this chip, which has 2.4 GHz output frequency, and power consumption 3.05 mW. Under the condition of maximum sub-sampling charge pump gain, the rms jitter is 2.39 ps, the phase noise is -103.9 dBc/Hz at 1 MHz. The die area is 0.80 mm2 and which the active core area is 0.018 mm2.
