| 摘要: | 隨著科技不斷演進，串列傳輸系統資料速率不斷提高，對於頻寬設計的難度也隨著提高，使用四階脈波振幅調變技術可以降低頻寬設計之難度，頻寬需求僅為非歸零訊號之一半。同時串列傳輸也取代了並列傳輸，例如USB、SATA、PCI-E、DisplayPort等皆使用串列傳輸系統介面。本論文參考Common Electrical Interface-28G-Very Short Reach (CEI-28G-VSR) 規格實現一個資料與時脈回復電路。
本論文參考CEI-28G-VSR實現一個使用四階脈波振幅調變的資料與時脈回復電路。並改善過去文獻之相位偵測器轉態源不足之問題，提出一個新的四階脈波振幅調變之全新轉態選擇器，使資料與時脈回復電路擁有較高的相位追索能力，且提高偵測資料邊緣型態能有效降低還原時脈抖動，本論文將四階脈波振幅調變之邊緣加以區分，把不具有參考性的邊緣忽略，避免引入不必要的時脈抖動。本論文中使用四分之一速率及波特率採樣的方式來降低整體功耗，本論文之電路設計採用TSMC 40 nm (TN40G) 1P10M CMOS 製程，輸入資料為20 Gbps PAM-4，還原時脈速率為2.5 GHz，操作電壓為0.9V，晶片面積為1.11 mm2，核心電路面積為0.135 mm2，還原時脈之峰對峰值18.9 ps，方均根值 2.73 ps，功率消耗為 17.52 mW。;The data rate of serial transmission systems keeps growing as technology progresses. In addition, bandwidth design becomes more difficult. The 4-level PAM-4 pulse amplitude modulation technology can be used to reduce the difficulty of the bandwidth design. The required bandwidth is halved compared to non-return-to-zero transmissions. Parallel transmission has been replaced at the same time by serial transmission. For instance, serial transmission system interfaces are used by USB, SATA, PCI-E, DisplayPort, and other devices. By reference to the Common Electrical Interface-28G-Very Short Reach (CEI-28G-VSR) specification, a data and clock recovery circuit is implemented in this article.
The CEI-28G-VSR is used in this research to create a data and clock recovery circuit employing 4-level PAM-4 pulse amplitude modulation. And, to address the previous literature′s problem of insufficient transition source of the phase detector, a new transition selector with fourth-order pulse amplitude modulation is proposed, so that the data and clock recovery circuit has a higher phase tracking ability, and improving the detection data edge type can effectively reduce the recovered clock jitter. In this thesis, the non-referential edges of the 4-level PAM-4 pulse amplitude modulation are ignored in order to avoid adding extra recovered clock jitter. In this thesis, the overall power consumption is decreased by quarter rate and baud rate sampling. The circuit of this thesis is designed in 40 nm standard CMOS process. The input data is 20 Gbps PAM-4, the recovery clock rate is 2.5 GHz, the supply voltage is 0.9V, the chip area is 1.11 mm2, the core area is 0.135 mm2, the peak-to-peak jitter of the recovery clock is 18.9 ps, and the RMS jitter of the recovery clock is 2.73 ps, with a power consumption of 17.52 mW. |
