本篇論文主要研製射頻收發機中之本地振盪源的相關電路，第二章的主要內容為操作在 C 頻段的 E 類功率振盪器以及操作在 K 頻段的差動 E 類功率壓控振盪器，上述兩個振盪器皆使用 E 類匹配網路來提高輸出功率，第三章是介紹操作在 K 頻段的鎖相迴路整合反射式調變器，第四章為操作在 K 頻段的四相位 E 類壓控振盪器。本篇論文的設計皆使用台積電 0.18 μm CMOS 實現。第二章主要介紹 E 類匹配網路的設計，首先會先設計出一 E 類功率放大器再透過回授方式滿足巴克豪森準則而穩定振盪，歸功於 E 類匹配網路，本次設計的振盪器輸出功率皆比傳統的交錯耦合對要大得多，E 類匹配網路的設計透過 E類負載公式以及負載遷移(Load pull)技術去最大化輸出功率和效率。而在本章分別設計了單端輸出以及差動輸出的功率振盪器，且操作在不同的頻段，藉此分析E 類匹配網路在不同頻率間的取捨以及考量。差動振盪器的設計是由單端振盪器透過交互耦接滿足巴克豪森準則而穩定振盪。本次電路以台積電 0.18 μm CMOS實現，單端輸出 E 類振盪器在 5.3 GHz 有 16.5 dBm 的輸出功率，距離載波偏移1 MHz 的相位雜訊為−122 dBc/Hz，整體電路優化指數 FOMP 為−212，晶片面積為 0.83×0.76 mm2；而差動輸出 E 類振盪器頻率範圍為 22.29-22.63 GHz，最大輸出功率為 13.6 dBm，距離載波偏移 1 MHz 的相位雜訊為−110 dBc/Hz，整體電路優化指數 FOMPOSC 為−198，晶片面積為 0.5×0.7 mm2。第三章是鎖相迴路整合反射式調變器，這個章節會介紹鎖相迴路的各個子電路以及使用轉移函數來分析迴路的穩定性，鎖相迴路中的振盪器是使用第二章設計的差動功率振盪器。在完成鎖相迴路的設計後接著整合反射式調變器。成功在24.2-24.6 GHz 完成量測，且量測不同 symbol rate 之下的 EVM。本章節以台積電0.18 μm CMOS 實現，量測的頻率範圍為 24.2-24.6 GHz，距離載波偏移 1 MHz 的相位雜訊為−105 dBc/Hz，量測到的最小方均根抖動量為 420 fsec，抖動的積分範圍為 1 kHz 到 40 MHz。全頻段的突波抑制量皆大於 60 dBc，鎖相迴路部分的電路優化指數 FOMN 為−231.63。而調變的部份我們首先量測 LO 抑制，全頻段的LO 抑制接大於 20 dBc，接續量測的是在不同 symbol-rate 之下的 BPSK 和 64-QAM 星座圖與頻譜，測得的 BPSK 和 64-QAM 最小 EVM 為 1.59 %，調變部分的優化指數 FOM 為 108，晶片面積為 1.01×1.4 mm2。 第四章為使用背閘極耦合技術實現之四相位 E 類功率振盪器。電路利用背閘極耦合技術將兩個差動輸出的振盪器進行四相位耦合，本章節會先介紹背閘極耦合技術，且會分析各種四相位耦合技術的優缺點，在使用背閘極耦合時我們有額外給予基體(Body)偏壓以便調整四相位耦合強度，我們也分析了不同的基體偏壓對電路效能的影響。在量測的部分會和大家介紹四相位的量測方法，而本次是使用四埠相量網路分析儀(VNA)操作在接收機模式(receiver mode)來進行四相位的量測。本章節以台積電 0.18 μm CMOS 實現，量測到的頻率範圍為 24.59-25.5 GHz，最大輸出功率為 13.4 dBm，距離載波偏移 1 MHz 的相位雜訊為−117.3 dBc/Hz，最小的相位誤差以及振幅誤差分別是 0.1°和 0.4 dB，優化指數 FOMQ達到−205，晶片面積為 1.04×0.9 mm2;This paper mainly develops the relevant circuits of the local oscillator source in the radio frequency transceiver. The main content of Chapter 2 is a C-Band Class-E power oscillator and a K-Band differential Class-E power voltage-controlled oscillator, which uses a Class-E matching network to increase output power. Chapter 3 introduces a K-band phase-locked loop integrated reflection-type modulator. Chapter 4 introduces a K-band quadrature Class-E voltage-controlled oscillator. The designs in this paper are all fabricated in TSMC 0.18 μm CMOS process. Chapter 2 will mainly introduce a Class-E matching network design. First, a Class-E power amplifier will be designed, and the oscillation will be stabilized by satisfying the Barkhausen criterion through the feedback method. Due to Class-E matching network, the output power of the proposed oscillator is much larger than the traditional cross-coupled pair. The Class-E matching network design is based on the Class-E load equations and load-pull technology to maximize output power and efficiency. In this chapter, power oscillators with single-ended output and differential output are designed respectively, which operate in different frequency bands to analyze the trade-offs and considerations of the Class-E matching network between different frequencies. The design of the differential oscillator is based on a single-ended oscillator that satisfies the Barkhausen criterion for stable oscillation through coupling. This circuit is fabricated in TSMC 0.18 μm CMOS process. The single-ended Class-E oscillator has an output power of 16.5 dBm at 5.3 GHz. The phase noise at 1 MHz offset frequency is −122 dBc/Hz. The FOMP of this work can reach to −212. The chip size is 0.83×0.76 mm2. The frequency range of the differential Class-E oscillator is 22.29-22.63 GHz, and the maximum output power is 13.6 dBm. The phase noise at 1 MHz offset frequency is −110 dBc/Hz. The FOMPOSC of this work reaches 198. The chip size is 0.5 × 0.7 mm2. Chapter 3 is the phase-locked loop integrated reflection-type modulator. This chapter will introduce the various circuits in the phase-locked loop and use the transfer functions to analyze the stability of the loop. The oscillator in the phase-locked loop is designed from Chapter 2. After completing the design of the PLL, the reflection-type modulator is then integrated. The EVM under different symbol rates is successfully measured at 24.2-24.6 GHz. This circuit is fabricated in TSMC 0.18 μm CMOS process. Between 24.2 and 24.6 GHz, the measured phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz is −105 dBc/Hz and 420 fs, respectively. The measured spur suppression is greater than 60 dBc in all frequencies. The FOMN of this work reaches -231.63. As for the modulation part, the LO suppression of all frequencies is greater than 20 dBc. We measured BPSK, 64-QAM constellation diagram as well as output spectrum with different symbol rates. The measured minimum EVMs for BPSK and 64-QAM modulation schemes are 1.59%. The FOM of this work can reach 108. The chip size is 1.01 × 1.4 mm2. Chapter 4 is a quadrature class-E power oscillator realized by back-gate coupling technology. The back gate coupling technology is used as the quadrature phase coupling between the oscillating pairs. This chapter will introduce the back gate coupling technology and analyze the advantages and disadvantages of various quadrature coupling technologies. When using back gate coupling, we have additionally given the body (Body) bias to adjust the quadrature coupling strength. We have also analyzed the influence of different body biases on the circuit performance. This circuit is fabricated in TSMC 0.18 μm CMOS process. The measured frequency range is 24.59-25.5 GHz, and the maximum output power is 13.4 dBm. The phase noise at 1 MHz offset frequency is -117.3 dBc/Hz. The minimum phase error and amplitude error are 0.1° and 0.4 dB, respectively. The calculated FOMQ is -205. The chip size is 1.04×0.9 mm2.
