混和訊號 1.6-3.6GHz 相位旋轉延遲鎖定迴路;A Mixed Signal 1.6-3.6GHz Phase Rotator Delay-Locked Loop In 40nm CMOS Technology

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/93572

請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/93572

題名:	混和訊號 1.6-3.6GHz 相位旋轉延遲鎖定迴路;A Mixed Signal 1.6-3.6GHz Phase Rotator Delay-Locked Loop In 40nm CMOS Technology
作者:	陸少綿;Lu, Shao-Mian
貢獻者:	電機工程學系
關鍵詞:	延遲鎖定迴路;延遲鎖相迴路;相位旋轉;DLL;Delay-Locked Loop;Phase Rotator
日期:	2024-01-11
上傳時間:	2024-09-19 17:20:10 (UTC+8)
出版者:	國立中央大學
摘要:	第五代雙倍資料傳輸同步動態隨機存取記憶體 (Gen-5 Double Data Rate Synchronous Dynamic Random Access Memory)[1]在維持和前代 DDR4/3 差不多的延遲時間(Latency Time)下，更強調超低工作功耗 (Power Consumption)和超大輸出入頻寬 (Input/Output (I/O)-Bandwidth)[2]，其中操作電壓進一步從 1.2V 下降到 1.1V，相比於 DDR4 相同模組比較下可帶來約 20%的功耗下降[3]，而 IO 頻寬來到 4800~6400 MT/s (並在後續更新中進一步提升)。在此超高資料傳輸效率和低電壓操作的條件下，訊號保真度(Signal Integrity)在遭遇先進製程產生的製程擾動和電性擾動的影響下將更難維持[4]，尤其是波形訊號的抖動 (Jitter)[5]和相位雜訊(Phase Noise)[6]更嚴重困擾高速電路設計，如在延遲鎖定迴路(Delay-Locked Loop)設計中，這些現象尤為突出。本文使用 40-nm CMOS 技術設計應對於 DDR5 DRAM 規格所需之 DLL 電路，希冀可解決高速傳輸所帶來的 Jitter 和 Phase Noise 相關議題，為 DDR5 DRAM 應用之市場普及做出貢獻。本文所設計之相位旋轉延遲線使用了一種直接輸入-輸出比較的技術，此技術與傳統的使用複製延遲的 DLL[7]相比，通過晶片內分割採樣時鐘將輸入時鐘的上升沿與輸出節拍時鐘對齊，可以最小化延遲線及複製延遲電路的使用，進而降低工藝-電壓-溫度（PVT）變異可能會引起複製延遲電路的延遲不匹配所產生的訊號抖動，同時也達到降低功耗的作用。最後完成的相位旋轉延遲鎖定迴路，其架構包含除頻器(Divider)、相位偵測器(Phase Detector)、計數器式控制電路(Counter-Based Controller)以及相位旋轉延遲線(Phase Rotator Delay Line)。操作頻率範圍在 1.6-3.6GHz，操作電壓 0.9V，鎖定週期為 40T，操作頻率 3.6GHz 時，消耗功率為 4.5mW，Jitterp-p 為 0.266ps，Jitterrms 為 0.188ps。 ;The fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR5 SDRAM) maintains a similar latency time to its predecessors DDR4 and DDR3. However, it emphasizes ultra-low power consumption and significantly increases input/output (I/O) bandwidth. [1] The operating voltage has further decreased from 1.2V to 1.1V, resulting in approximately a 20% reduction in power consumption compared to DDR4 modules with the same capacity. The I/O bandwidth has reached speeds of 4800-6400 MT/s, with further improvements expected in subsequent updates. Under these conditions of ultra-efficient data transfer and low voltage operation, signal integrity becomes more challenging to be kept in the same shape due to process and electrical disturbances associated with advanced fabrication processes. This is particularly prominent in high-speed circuit design, notably in the design of the Delay-Locked Loops (DLL). This paper presents the design of a DLL circuit for DDR5 SDRAM specifications using 40-nm CMOS technology, and aimes at addressing jitter and phase noise issues associated with high-speed transmission, which contributes to the adoption of DDR5 SDRAM in the market. The phase-rotator delay line used in this paper employs a direct input-output comparison technique. This approach, compared to the traditional use of duplicated delay line in DLLs, minimizes the use of delay line and duplicate delay circuits by aligning the rising edges of the input clock with the output clock within the chip′s internal sampling clock. These design efforts does not only minimize signal jitter caused by variations in delay within duplicate delay circuits due to process-voltage temperature (PVT) variations but also reduces power consumption. iii The final phase-rotator delay-locked loop consists of a divider, phase detector, counter-based controller, and phase-rotator delay-lines. It operates in the frequency range of 1.6-3.6GHz with a voltage of 0.9V and a lock period of 40T. At an operating frequency of 3.6GHz ; it consumes 4.5mW and has a jitter peak-to-peak of 0.266ps, and a root mean square jitter of 0.188ps.
顯示於類別:	[電機工程研究所] 博碩士論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
index.html		0Kb	HTML	12	檢視/開啟

在NCUIR中所有的資料項目都受到原著作權保護.

社群 sharing

資料載入中.....