本論文提出具寬操作頻率範圍之數位式鎖相迴路，其架構採用數位迴路濾波器取代由電阻及電容所組成之被動濾波器，以達到降低面積之效果；同時利用降低數位迴路濾波器取樣頻率之方法，使其在輸入參考頻率與除頻器之除數同時變動時，鎖相迴路系統皆為穩定操作。其中，使用所提出的具有電流級距控制器之數位至電流轉換器，除了使數位控制振盪器之轉換增益較為線性外，同時也可提高其頻率調控之解析度，達成低時脈抖動之設計。 此數位式鎖相迴路採用台積電 0.18 um 1P6M CMOS製程實現，並經由量測驗證其操作頻率範圍可達到200 MHz至1.4 GHz，且在操作頻率為800 MHz時，其峰對峰時脈抖動量(peak-to-peak jitter)為4.6%。其在供應電壓為1.8 V且輸出時脈為1 GHz之操作下消耗功率為7.27 mW，核心面積為0.04 mm2。此數位式鎖相迴路在與相同輸出頻率的倍頻範圍條件相比下，所耗費之面積極小，因此極為適合於系統晶片之應用。 In this thesis, a digital phase-locked loop (DPLL) with the wide operating range is presented. The architecture of the proposed DPLL uses a digital loop filter to replace passive loop filter for area saving purpose. The DPLL maintains the system stability by reducing the sampling frequency when the reference clock and the multiplication factor are varied. The linearity of the gain and timing resolution of digital-controlled oscillator are improved by using the proposed digital-to-current converter with current-step controller (CSC). Thus, the CSC used here can enhance the jitter performance. The proposed DPLL is implemented in a 0.18-um TSMC 1P6M CMOS process. It can operate from 200 MHz to 1.4 GHz and has a 4.6% peak-to-peak jitter at 800 MHz. The power consumption and the core area are 7.27 mW at 1 GHz and 0.04 mm2, respectively. In this work, the proposed DPLL can obtain the small area cost under the same multiplication range. Therefore, it is useful for system on chip (SoC) systems.
