A 2-V 7.2 degrees jitter AM-suppression CMOS amplifier using current-mode hybrid magnitude control

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題名:	A 2-V 7.2 degrees jitter AM-suppression CMOS amplifier using current-mode hybrid magnitude control
作者:	Huang,KH;Wang,WC;Yang,TH;Wang,CK
貢獻者:	電機工程研究所
關鍵詞:	LIMITING AMPLIFIER
日期:	1999
上傳時間:	2010-06-29 20:20:17 (UTC+8)
出版者:	中央大學
摘要:	This paper proposes an AM-suppression CMOS amplifier that incorporates a discrete-level automatic gain control (AGC) with a hysteresis hard limiter in order to reduce magnitude-dependent jitter and speed up AM-suppression response. The gain control that is composed of a transition-based magnitude controller and a discrete-level current-mode variable gain amplifier (VGA) does not require coherent detection and external components. The prototype amplifier demonstrates a jitter of 7.2 degrees from 1-Mb/s pulse-point modulated (PPM) data input with 20-dB dynamic range (40-400 mV(pp)), which is six times improvement over the conventional limiter alone approach, The amplifier with an active area of 0.64 mm(2) is implemented in 0.8-mu m single-poly double-metal digital CMOS technology. It consumes 18 mW from a single 2-V supply.
關聯:	IEEE JOURNAL OF SOLID-STATE CIRCUITS
顯示於類別:	[電機工程研究所] 期刊論文

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