Verification of 1D BJT numerical simulation and its application to mixed-level device and circuit simulation

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > journal & Dissertation > Item 987654321/32509

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/32509

Title:	Verification of 1D BJT numerical simulation and its application to mixed-level device and circuit simulation
Authors:	Chang,CC;Dai,JF;Tsai,YT
Contributors:	電機工程研究所
Keywords:	INCOMPLETE LU METHOD
Date:	2003
Issue Date:	2010-07-06 18:30:13 (UTC+8)
Publisher:	中央大學
Abstract:	In this paper, we study on a 1D BJT model, which saves the memory size and computation time and verify that the characteristic of 1D BJT model is in good agreement with 2D BJT model. We use the equivalent circuit approach to simulate the BJT device. Poiss
Relation:	INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	446	View/Open

社群 sharing