中大機構典藏-NCU Institutional Repository-提供博碩士論文、考古題、期刊論文、研究計畫等下載:Item 987654321/69043
English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 66984/66984 (100%)
造访人次 : 22924262      在线人数 : 103
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻


    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/69043


    题名: 使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路;All-Digital Clock De-Skew Circuit with Adaptive Loading Using Reused Delay Measurement Technique
    作者: 蔡佳銘;Tsai,Chia-ming
    贡献者: 電機工程學系
    关键词: 全數位;時脈偏移校正電路;負載自適應;同步複製延遲電路;all-digital;de-skew circuit;adaptive loading;synchronous mirror delay
    日期: 2015-08-28
    上传时间: 2015-09-23 15:11:58 (UTC+8)
    出版者: 國立中央大學
    摘要: 本論文提出了一個能隨時根據輸出負載變化進行鎖定修正,並且使用重複延遲量測技術來減少電路面積的新式全數位時脈偏移校正電路。能夠隨時根據輸出負載變化進行鎖定修正這點改善了一般同步複製延遲電路只能用於固定負載的缺點,另外使用重複延遲量測技術則達成了只使用單一硬體的架構來取代掉傳統同步複製延遲電路架構中單調、重複性高、卻又佔用了大量面積的量測延遲線,進一步的減少電路面積,更加強化同步複製延遲電路面積小的優點。
    本論文所實現的使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路是使用90 nm製程來製作設計,整體晶片的總面積為955 × 955 um2,其中核心電路的面積為106 × 80 um2,操作電壓為1 V,可用的操作頻率範圍為0.34 – 1.8 GHz,功率消耗在操作頻率為1.8 GHz時為6.4 mW。電路的鎖定時間為最多19個週期,鎖定後的輸出時脈訊號在各種操作頻率下最大靜態相位誤差為20.58 ps,方均根抖動量為2.42 ps,峰對蜂抖動量為18.89 ps。;In this thesis, a modern all-digital clock de-skew circuit is proposed. It not only can be calibrated by itself according to the variation of output loading, but also be reduced the area by the reused delay measurement technique. The application of the conventional SMD is restricted because it can only be used with a fixed output loading, but now the proposed all-digital clock de-skew circuit is no longer be restricted because it can be calibrated by itself according to the variation of output loading. The measurement delay line of conventional SMD is monotonous, repeated, but costs a lot of area, so this study proposed the reused delay measurement technique. The reused delay measurement technique is reusing only a single unit of hardware to measure the time difference instead of using the measurement delay line, so it can cost less area and enhance the advantage of the SMD.
    This study was implemented by 90 nm process. The area of whole chip is 955 × 955 um2, and the area of the core circuits is 106 × 80 um2. The supply power voltage is 1 V, and the operating frequency is 0.34 GHz to 1.8 GHz. The power consumption at 1.8 GHz is 6.4 mW. The locking time is less than 19 cycles, and the maximum of the static phase error is 20.58 ps, the rms jitter is 2.42 ps, and the peak-to-peak jitter is 18.89 ps.
    显示于类别:[電機工程研究所] 博碩士論文

    文件中的档案:

    档案 描述 大小格式浏览次数
    index.html0KbHTML328检视/开启


    在NCUIR中所有的数据项都受到原著作权保护.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回馈  - 隱私權政策聲明