使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路;All-Digital Clock De-Skew Circuit with Adaptive Loading Using Reused Delay Measurement Technique

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題名:	使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路;All-Digital Clock De-Skew Circuit with Adaptive Loading Using Reused Delay Measurement Technique
作者:	蔡佳銘;Tsai,Chia-ming
貢獻者:	電機工程學系
關鍵詞:	全數位;時脈偏移校正電路;負載自適應;同步複製延遲電路;all-digital;de-skew circuit;adaptive loading;synchronous mirror delay
日期:	2015-08-28
上傳時間:	2015-09-23 15:11:58 (UTC+8)
出版者:	國立中央大學
摘要:	本論文提出了一個能隨時根據輸出負載變化進行鎖定修正，並且使用重複延遲量測技術來減少電路面積的新式全數位時脈偏移校正電路。能夠隨時根據輸出負載變化進行鎖定修正這點改善了一般同步複製延遲電路只能用於固定負載的缺點，另外使用重複延遲量測技術則達成了只使用單一硬體的架構來取代掉傳統同步複製延遲電路架構中單調、重複性高、卻又佔用了大量面積的量測延遲線，進一步的減少電路面積，更加強化同步複製延遲電路面積小的優點。本論文所實現的使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路是使用90 nm製程來製作設計，整體晶片的總面積為955 × 955 um2，其中核心電路的面積為106 × 80 um2，操作電壓為1 V，可用的操作頻率範圍為0.34 – 1.8 GHz，功率消耗在操作頻率為1.8 GHz時為6.4 mW。電路的鎖定時間為最多19個週期，鎖定後的輸出時脈訊號在各種操作頻率下最大靜態相位誤差為20.58 ps，方均根抖動量為2.42 ps，峰對蜂抖動量為18.89 ps。;In this thesis, a modern all-digital clock de-skew circuit is proposed. It not only can be calibrated by itself according to the variation of output loading, but also be reduced the area by the reused delay measurement technique. The application of the conventional SMD is restricted because it can only be used with a fixed output loading, but now the proposed all-digital clock de-skew circuit is no longer be restricted because it can be calibrated by itself according to the variation of output loading. The measurement delay line of conventional SMD is monotonous, repeated, but costs a lot of area, so this study proposed the reused delay measurement technique. The reused delay measurement technique is reusing only a single unit of hardware to measure the time difference instead of using the measurement delay line, so it can cost less area and enhance the advantage of the SMD. This study was implemented by 90 nm process. The area of whole chip is 955 × 955 um2, and the area of the core circuits is 106 × 80 um2. The supply power voltage is 1 V, and the operating frequency is 0.34 GHz to 1.8 GHz. The power consumption at 1.8 GHz is 6.4 mW. The locking time is less than 19 cycles, and the maximum of the static phase error is 20.58 ps, the rms jitter is 2.42 ps, and the peak-to-peak jitter is 18.89 ps.
顯示於類別:	[電機工程研究所] 博碩士論文

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