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    "CHENG, Kuo-Hsing"的相關文件 

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    顯示 8 項.

    類別 日期 題名 作者 檔案
    [電機工程學系] 期刊論文 2016-06-01 Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture 鄭國興; CHENG, Kuo-Hsing; LIU, Jen-Chieh; TU, Yo-Hao
    [電機工程學系] 期刊論文 2015-12-22 A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC 鄭國興; Tu, Yo-Hao; Huang, Hong-Yi; Cheng, Kuo-Hsing; Liu, Jen-Chieh; Hu, Chang-Chien
    [電機工程學系] 期刊論文 2014-08-01 A 0.9-to 8-GHz VCO with a differential active inductor for multistandard wireline SerDes 鄭國興; Cheng, Kuo-Hsing; Hung, Cheng-Liang; Alex Gong, Cihun-Siyong; Liu, Jen-Chieh; Jiang, Bo-Qian; Sun, Shi-Yang
    [電機工程學系] 期刊論文 2014-08-01 A 0.9-to 8-GHz VCO with a differential active inductor for multistandard wireline SerDes 龔存雄; Cheng, Kuo-Hsing; Hung, Cheng-Liang; Alex Gong, Cihun-Siyong; Liu, Jen-Chieh; Jiang, Bo-Qian; Sun, Shi-Yang
    [電機工程學系] 期刊論文 2013-03-01 A wide supply voltage range and low-power all-digital clock generator 鄭國興; Cheng, Kuo-Hsing; Liu, Jen-Chieh; Huang, Hong-Yi; Chen, Yu-Tso
    [電機工程學系] 期刊論文 2012-12-01 A 0.6-V 800-MHz all-digital phase-locked loop with a digital supply regulator 鄭國興; Cheng, Kuo-Hsing; Liu, Jen-Chieh; Huang, Hong-Yi
    [電機工程學系] 期刊論文 2012-01-01 A 50 ns verify speed in resistive random access memory by using a write resistance tracking circuit 鄭國興; SHEU, Shyh-Shyuan; CHENG, Kuo-Hsing; CHEN, Yu-Sheng; CHEN, Pang-Shiu; TSAI, Ming-Jinn; LO, Yu-Lung
    [電機工程學系] 期刊論文 2012-01-01 An all-digital clock synchronization buffer with one cycle dynamic synchronizing 鄭國興; Cheng, Kuo-Hsing; Hong, Kai-Wei; Hsu, Chi-Fa; Jiang, Bo-Qian

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